This invention involves floating gate memory devices known as flash EEPROM. Flash EEPROM can be programmed by hot-electron injection and erased by Fowler-Nordheim electron tunneling.
There are two types of hot-electron injection EEPROM cells classified by the injection locations; they are referred to as "drain-side" injection cells and "source-side" injection cells. In a drain-side injection cell, hot-electrons are injected onto the floating gate from a point in the source-drain channel nearest the drain-side; while in a source-side injection cell, hot-electrons are injected onto the floating gate from a point in the source-drain channel nearest the source-side.
Typical drain-side injection cells require a structure with a conduction channel and a control-gate stacked on top of a floating gate. FIG. 1 shows a typical drain-side injection cell comprising a substrate 10, a source region 12, a drain region 14, a floating gate 16, and a control-gate 18. The three major operating terminals in this cell are the drain, the source, and the control-gate. In this figure, for clarity, the isolating dielectric layers are not shown between the various elements. In this structure a conduction channel 20, located between the source region 12 and the drain region 14, is covered by the floating gate 16. During programming, the drain-side injection takes place under the floating gate 16 at a point 13 nearest the drain 14.
Drain-side injection cells are often referred to as "single-channel", or "one-transistor" cells, because from the hot-electron generation point of view, a minimum of only one channel section is all that required to produce the drain-side hot-electrons injections. However, in practical applications, as appeared in various prior art, some drain-side injection cells were designed with additional serial channels or split-gates for the purposes of avoiding drain-to-source "short-channel punchthrough" vulnerability, or of overcoming the so-called "overerased" shortcoming existing in flash memory cells fabricated using "dual-polysilicon" process.
Source-side injection cells differ structurally and functionally from drain-side injection cells. A minimum of two serial channel sections are required for a source-side injection cell. Source-side injection cells can be constructed by modifying or extending the source-end of a one-transistor cell structure to include either: (1) a split-gate at the source-side of the simple single-channel cell such as in U.S. Pat. Nos. 5,280,446 and 5,278,439 per Ma et al., and U.S. Pat. No. 5,029,130 per Bing Yeh; or (2) a separate gate at the source-side of a single-channel cell such as papers in IEDM pp. 603-606, 1989 per Naruke et al., and IEDM pp. 319-322, 1991 per Yamauchi et al. In either case, a serial channel must be added immediately next to the source-side of the floating gate channel.
FIG. 2 shows a typical split-gate source-side injection cell comprising a p-type substrate 30, an n-type source region 32, an n-type drain region 34, a floating gate 36, a control-gate 38, a select-gate 40, a select-gate channel region 42 (that is the added serial channel 42), and a transitional channel region 44. The four major operating terminals in this cell are the drain, the source, the control-gate, and the select-gate. Again, for clarity, no isolating dielectric layers are shown between the various elements. The source-side injection takes place under the floating gate 36 at a point near the transitional channel 44. Note that the transitional channel 44 of FIG. 2 corresponds to the source terminal 12 of FIG. 1, hence dubbed the term "source-side injection."
The programming speeds of source-side injection cells and drain-side injection cells are comparable. However, a major difference between the source-side injection and the drain-side injection exists in the channel current requirements for programming the cells. That is, source-side injection cells require much less current to program than do drain-side injection cells.
The Kazerounian et al. U.S. Pat. No. 5,042,009 teaches a method for drain-side injection programming a floating gate transistor with a markedly reduced channel current. This patent shows a cell comprising a two-section channel region between a pair of associated source and drain regions. The channel region includes a first portion under a floating gate which is heavily doped and a second portion adjacent the source region which is more lightly doped. The device taught by Kazerounian et al. has only two polysilicon gates and it is programmed by a drain-side injection mechanism; it is therefore not adaptable to the type of memory array devices with which the present invention is intended to be used. Furthermore, as will become more evident in the following sections, the two channel portions described in the Kazerounian et al.'s dual-polysilicon cells must be doped in the opposite order of concentrations for threshold voltage adjustments in comparison to the present invention. This is due to the completely different underlying operation mechanisms between "dual-polysilicon" drain-side injection memory devices and a "triple-polysilicon" source-side injection memory devices.